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翻訳と辞書　辞書検索 [ 開発暫定版 ] スポンサード リンク Espresso heuristic logic minimizer ： ウィキペディア英語版 Espresso heuristic logic minimizer The Espresso logic minimizer is a computer program using heuristic and specific algorithms for efficiently reducing the complexity of digital electronic gate circuits. Espresso was developed at IBM by Robert Brayton. Richard Rudell later published the variant Espresso-MV in 1986 under the title "Multiple-Valued Logic Minimization for PLA Synthesis". Espresso has inspired many derivatives. == Introduction == Electronic devices are composed of numerous blocks of digital circuits, the combination of which performs the required task. The efficient implementation of logic functions in the form of logic gate circuits (such that no more logic gates are used than are necessary) is necessary to minimize production costs, and/or maximize a device's performance. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Espresso heuristic logic minimizer」の詳細全文を読む スポンサード リンク 翻訳と辞書 : 翻訳のためのインターネットリソース Copyright(C) kotoba.ne.jp 1997-2016. All Rights Reserved.